1. Technical Field
The disclosure relates to an electronic device package structure and a method for fabricating the same, and in particular relates to an electronic device package structure with a hydrophilic polymer protection layer and a method for fabricating the same.
2. Technical Art
To continue improvements in mass production of packaged electronic devices, a main manufacturing trend is to utilize low dielectric constant (k) dielectric layers in the interconnection structure of a manufactured chip. By using a low k dielectric layer, parasitical capacitance in the interconnection structure of a manufactured chip may be minimized. Nevertheless, low k dielectric layers have a very low Young's modulus. Also, low k dielectric layers have poor adhesion characteristics and low CTE matching ability with other materials. Additionally, low k dielectric layers are easily damaged due to thermal or mechanical stress. Moreover, low k dielectric layers are easily affected by humidity and temperature and may easily absorb moisture during wet processes such as a through silicon via (TSV) electro plating process. Also, electronic devices with low k dielectric layers may succumb to electromigration degradation due to Joule heating and back stress.
Thus, a novel electronic device package structure and a method for fabricating the same are desired to maintain integrity of low k dielectric layers after a wafer bonding process, comprising a through hole formation process, an electro plating filling process, a thermal bonding process or a wafer cutting process, is performed thereto.